The present disclosure relates generally to analog-to-digital converters (ADCs), and more particularly to delta-sigma (ΔΣ) ADCs with reduced DC offset and reduced low frequency noise.
A delta-sigma (ΔΣ) ADC is similar to a voltage controlled oscillator in which the frequency of the oscillation is proportional to the input voltage. A ΔΣ ADC is typically realized with a ΔΣ modulator, such as is represented in FIG. 1. A ΔΣ modulator 100 operates on an analog input to a difference operator 102, such as may be implemented as a summing junction. An integrator 104 operates on the error signal produced by difference operator 102. A comparator 106 provides a threshold operation in which the output of integrator 104 is compared to a threshold, and an output of comparator 106 changes state when the threshold is crossed. A latch 108, which can be implemented as a D flip-flop, captures the output of comparator 106 and produces a bit stream output. A feedback loop is provided through a one bit digital-to-analog converter (DAC) 110. The output of DAC 110 is provided to difference operator 102 to produce the error signal applied to integrator 104. The bit stream produced by delta-sigma modulator 100 is used to provide an analog-to-digital conversion when the bit stream output pulses are counted within a given time interval. When the pulses output from latch 106 are counted or summed over a given interval, the digitized value of the count or sum represents an average of the analog input. Feedback DAC 110 typically converts a bit stream value output from latch 108 to a voltage reference that can represent a range of operation for the delta-sigma modulator. Comparator 106 and latch 108, when combined, can be viewed as providing a quantization operation.
When delta-sigma modulators are used to convert analog inputs to a bit stream output for use in ADC applications, such a ΔΣ ADC may be limited in the dynamic range and the acceptable frequency of the analog input. The accuracy of high dynamic range DC and low frequency measurement signal chains in a ΔΣ ADC are dominated by DC offset and 1/f noise. The input and signal chains in a ΔΣ ADC are typically implemented as differential pathways to contribute to rejecting or reducing noise.
Auto-zeroing and chopping are two fundamental approaches conventionally used to minimize DC offset and low frequency noise in data converters and sampled amplifiers. Auto-zeroing refers to a technique for reducing the impact of DC offsets associated with ADC operation by measuring and attempting to cancel offsets. In one approach, ADC inputs are shorted and the DC, input-referred, offset is measured, stored and subtracted from input values during regular operation. This approach is limited by the accuracy of measuring the offset and residual errors during the cancellation of the offset.
Chopping refers to a technique for switching signal pathways in an attempt to compensate for the impact of pathway mismatches. Signal pathway mismatches may be related to component tolerances, manufacturing processes, trace paths and other mismatched items that can produce voltage offsets in the signal pathways. Chopping helps to remove the offsets by alternating signal pathways to balance mismatch impact over time.
However, notwithstanding the above techniques, a residual DC offset continues to be present due to mismatches in the differential signal paths. Achieving an input referred offset in the range of 100 nV is a major challenge in high accuracy DC measurement circuits.
Referring to FIG. 2, a diagram of a charge domain model of a typical first order ADC system 120 that is based on a ΔΣ modulator, such as that illustrated in FIG. 1, is illustrated. System 120 illustrates the charge domain operation of the first order ΔΣ ADC that shows offset sources associated with integrators and switches. System 120 illustrates an input sampling capacitor Cs, a feedback sampling capacitance Cref, an integration and amplification capacitance Cint and a quantizer 122. The offset charge associated with each of these signal paths are illustrated as Qoff_in across input sampling capacitance Cs, Qoff_dac across feedback capacitance Cref, Qoff_int associated with the integrator, and offset Voff_quant associated with quantizer 122. The input referred offsets associated with the sources modeled and reflected to the input in system 120 are summarized in Equation 1 below.
                              V          off_tot                =                                            Q              off_in                        Cs                    +                                    Q              off_dac                        Cs                    +                                    Q              off_int                        Cs                    +                                    V              off_quant                        ·                          (                              1                -                                  z                                      -                    1                                                              )                                +                      V            off_int                                              (        1        )            
Equation 1 indicates that offsets associated with the input and the feedback DAC, as well as the amplifiers, refers to the ADC input as is, and therefore a reduction in the amplifier offset and 1/f noise contribution is insufficient to reduce the input offset.
In known ADCs, attempts have been made to remove DC offsets by focusing on amplifier offsets and 1/f noise. One approach to reduce or remove DC offsets calls for the introduction of a chopping operation as described above. With this approach, a signal path is modulated and demodulated with switches or pulse signals to chop the signal. The chopping operation can contribute to reducing DC offsets and low frequency noise in an integrator/amplifier. These approaches, however, do not address residual errors that originate from the chopping activity itself.
One known attempt to reduce DC offsets and 1/f noise associated with switched capacitor gain stages, as well as ΔΣ ADCs, employs a fast chopping switch before and after the integrator, which tends to move the low frequency errors to higher frequencies and permits the useful signal to pass unchanged.
Referring now to FIG. 3, a block diagram of a conventional chopped integrator used with a ΔΣ ADC is illustrated as system 130. An operational trans-conductance amplifier (OTA) 132 with a gain of gme has an input chopper 134 and an output chopper 135. Input and output choppers 134, 135 move 1/f noise and DC offsets of OTA 132 to a higher frequency. For example, a DC offset of OTA 132, represented as voltage Voff_amp is moved to a higher frequency by choosing a chopping frequency, fchop_fast, which moves 1/f noise away from the useful signal.
Sampling switches 136, 138 and feedback DAC switches 137a, 137b have a charge injection that is common mode if the switches are ideally matched. Sampling switches 138 are referenced to a common mode voltage Vcm to provide common mode sampling in an arrangement sometimes referred to as parasitic insensitive sampling. However, mismatches in the paths and switch variables tend to produce a DC offset voltage Voff_int, which is temperature dependent. As indicated in FIG. 3, the accumulated DC offset Voff_int equals the sum of the DC offset Voff_samp from sampling switches 136 and the DC offset Voff_dac from the feedback DAC switches 137a, 137b. DC offset Voff_dac can also be influenced by mismatches in feedback capacitors 133a, 133b. The DC offset represented by voltage Voff_dac can be dynamic based on the density of the logic ones produced by the ADC provided in the DAC feedback. The dynamic nature of voltage Voff_dac can be further influenced by mismatches in the DAC switches. The DC offset due to a high logic one density in the output of the ADC tends to decrease for analog inputs around midrange of the ADC. Switch leakage mismatch, both junction and off-state, also contributes to offset errors.
FIG. 4 illustrates a system block diagram of a charge domain model of a ΔΣ ADC using a chopped integrator such as that shown in FIG. 3. A shortcoming of the technique of using a fast chopping clock before and after the integrator, as illustrated in FIG. 4, is that charge injection mismatches due to input and feedback switches of the ADC continue to remain a dominant offset source.
FIG. 5 illustrates another known attempt to reduce DC offset and 1/f noise to push the input signal to a high frequency using an input chopping network. The high pass quantization noise generated by a typical ΔΣ ADC can contaminate the input signal in accordance with this approach. The contamination can be reduced by converting the low pass ΔΣ modulator to a high pass modulator using the low pass-to-high pass frequency transformation z→-z. This is the approach is illustrated in the system block diagram shown in FIG. 5. In the modulator illustrated in FIG. 5, unlike previous ΔΣ ADCs, the quantization noise is pushed to lower frequencies. However, due to primary modulation at the input, the useful signal is pushed to higher frequencies, generating stringent settling time and slew rate requirements on the analog modulator, which tends to increase overall power consumption for the ADC. In addition, residual offset due to the fast chopping activity at the input continues to present a problem with inaccuracy in this architecture.
Another known approach to address DC offsets is similar to that described above in FIG. 5, with the addition of a slow chopper to remove residual DC offset. FIG. 6 illustrates a charge domain model with an ADC incorporating a slow chopper. The ADC of FIG. 6 has the drawback that a slow changing input is processed to a very high frequency, which tends to increase the analog modulator settling and slew rate requirements. In addition, moving the input signal to a higher frequency tends to cause a disturbance on the integration capacitor. The disturbance on the integration capacitor reduces the DC accuracy of the ADC, which in turn contributes to a reduction in the overall accuracy of the ADC. The ADC charge domain model exhibits a lack of phase inversion in the feedback DAC, which makes this approach less useful in terms of limitations on DC accuracy and dynamic range.